(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of early detection of plasma/charging damage in the fabrication of integrated circuit devices.
(2) Description of the Prior Art
The manufacture of large scale integrated circuits involves hundreds of processing steps. Most of these processing steps involve depositing layers of material, patterning them by photolithographic techniques, and etching away the unwanted portions. Plasma etching processes are often used because they are dry processes and they provide the cleanliness and degree of control required in integrated circuit manufacture.
The most important semiconductor device in current technology is the metal-oxide-silicon field effect transistor (MOSFET). This device consists of two shallow regions of one type semiconductor—the source and drain—seperated by a region of another type—the channel region. A gate electrode overlies the channel region and is separated from it by a thin gate oxide layer. This thin gate oxide layer is one of the most critical components of the MOSFET. Typically, the gate oxide layer is thermally grown silicon oxide having a thickness on the order of 70-150 Angstroms in the current 0.25 micron design rule. An insulating film this thin is highly susceptible to damage such as from ion and electron bombardment from plasmas during backend processing. Plasma-induced degradation of gate oxide reliability is a key issue in achieving high performance MOSFET's.
The multiple exposures of gate oxides to steps involving plasmas has led to the emergence of several test structures designed to amplify the charging exposure and thereby allow proper and timely assessment of damage caused by the plasma processing steps. Plasma damage test structures are discussed in Silicon Processing for the VLSI Era, Vol. 3, by S. Wolf, Lattice Press, Sunset Beach, Calif. (1995) pp. 507-9. The conventional test structures fall into one of two categories: 1) antenna structures which have large areas of conductor exposed to plasma as compared to area of gate oxide, and 2) large area capacitors which are formed over the gate oxide. In addition, both types of structures may be either edge-intensive or area-intensive. However, it is difficult for these structures to catch plasma-induced damage in a timely manner if the damage is very slight.
A number of patents have addressed the plasma-induced damage issue. U.S. Pat. No. 5,650,651 to Bui discloses a plasma damage reduction device. U.S. Pat. No. 5,781,445 describes a plasma damage test structure consisting of a MOSFET surrounded by a conductive shield grounded to the substrate. U.S. Pat. No. 5,596,207 to Krishnan et al discloses a modified MOS structure having conductive sidewalls over a gate used to test for plasma damage. U.S. Pat. No. 5,638,006 to Nariani et al teaches the use of a testing structure that can differentiate weak oxide from charge-damaged oxide using an antenna structure.